Traditionally, in IC devices based on 28 nm and earlier technology nodes, doped polysilicon may be used for gate material as well as for FEOL gate resistors. In devices using metal gates, such as 22 nm fully depleted silicon on isolator (FDSOI) devices, a middle-of-line (MOL) RM resistor is used as a FEOL resistor; however, additional RM processes and a thicker interlayer dielectric layer in a MOL substrate stack may be necessary causing fabrication complexities. Nevertheless, the MOL resistor is necessary since resistance of the metal gate material (e.g., titanium nitride (TiN), tungsten (W), etc.) may be lower than doped polysilicon and, therefore, unable to provide sufficient resistance as a gate resistor. For controlling the gate resistance through gate patterning, sufficiently thin metal lines may be unachievable due to photolithography process limitations. Also, a height of the gate may be based on a minimum height of a gate fin and metal fill.
A need therefore exists for methodology enabling fabrication of a metal gate resistor structure as a FEOL resistor in devices using metal gate technology.